Analog-to-Digital converter (ADC) is an essential building block in any of communication system to convert a received analog signal to a corresponding digital format for data processing or to recover the received digital signal. With the advance of communication systems in recent years, the speed requirement of data transition is getting into territory of tens of Giga bit per second (Gbps). For example, fourth generation serial-deserializers (Gen-4 Serdes) or 5G communication system process data in 10s of Gbps. This data speed increase directly results in the ADC operational speed increase to tens of Giga sample per second (Gsps).
Time-interleave architecture becomes useful and popular among industry pioneers to fulfill the ADC speed requirement from high-speed communication systems since the operational speed of a standalone ADC can achieve merely up to 2 Gsps even with the development of circuit techniques and process technologies. However, due to the usage of multiple ADCs in a time-interleave architecture, the offset, gain, and timing skew mismatches from environment (e.g., temperature, voltage, drift etc.) or manufacturing variation between these ADCs can cause significant performance degradation.